**Mux Error in NV_Register_Combiners**

This is to report that there are several documents on the Nvidia Register combiners that incorrectly state the effect of using MUX as a General Combiner Output.

(This includes the Nov. 11, 1999 Nvidia “Combiners.pdf” doc, which has excellent diagrams of the GeForce register combiner extension, but lists that Mux uses ((Tex0.alpha > 0.5 )? ab : cd ) ). As well as the “RegisterCombiners.pdf” which lists ((Spare0.alpha >= 0.5) ? ab : cd ).

From every test i’ve run, using 6.18 drivers, enabling MUX output gives

(Spare0.alpha < 0.5)?ab :cd


thats written in the newer specs (newer than 1999 )

there they wrote that they always wrote it the wrong way around and that they sorry about it…

Yeah that is a bug in some of the earlier docs. I think is was a slip of the mind, because the initial value of spare0.alpha is actually tex0.alpha (if enabled), thus in the first combiner the mux essentially does use tex0.alpha…

As for the inequality, I thought greater than is correct, but Im not sure. I would have to doublecheck to make sure.

Yes, old specs had the wrong formula. This should be fixed in the latest spec revision. Hopefully we can get some fixed versions of the other documents posted.

  • Matt