This is to report that there are several documents on the Nvidia Register combiners that incorrectly state the effect of using MUX as a General Combiner Output.
(This includes the Nov. 11, 1999 Nvidia “Combiners.pdf” doc, which has excellent diagrams of the GeForce register combiner extension, but lists that Mux uses ((Tex0.alpha > 0.5 )? ab : cd ) ). As well as the “RegisterCombiners.pdf” which lists ((Spare0.alpha >= 0.5) ? ab : cd ).
From every test i’ve run, using 6.18 drivers, enabling MUX output gives
(Spare0.alpha < 0.5)?ab :cd