Correct usage of Kernel execution mode


#1

What is the correct and intended way to use the SPIR-V Kernel execution mode?

My main use case is based around using Vulkan to create a pipeline with a SPIR-V compute kernel at its core (no other pipeline stages, just a single compute stage). However, I am struggling to find out how to utilise the data that is on my device from inside the entry point of my compute kernel. I can see how to use Vulkan to create memory buffers on the device, and I can see how I can copy data in to and out of these memory buffers (transfers between host and device), but I can see no way to tell my SPIR-V code that these memory buffers exist and that these particular variables should be associated with those particular memory buffers.

Can anyone shed any light on how this is supposed to work?

Can anyone also shed any light on what the intended use cases of a compute kernel and the kernel execution mode are meant to be?


#2

What is the correct and intended way to use the SPIR-V Kernel execution mode?

In Vulkan? You don’t. Vulkan does not support the Kernel execution model of SPIR-V, just like OpenCL doesn’t support the 5 shader or GLCompute execution models.

If you just want to do computations, you use the GLCompute execution model.

I can see no way to tell my SPIR-V code that these memory buffers exist and that these particular variables should be associated with those particular memory buffers

That’s what descriptors are for. There’s a whole chapter on it in the Vulkan specification.


#3

What is the Kernel execution model for then? How is one supposed to use it?


#4

SPIR-V is used in both OpenCL and Vulkan. OpenCL allows the use of Kernel execution models and forbids the use of the shader execution modes and GLCompute. Vulkan does the opposite.

Basically, both OpenCL and Vulkan needed an intermediate language, and they had need for about 95% of the same constructs. But there were some things unique to each one. So they share the same language, but you cannot shove the same SPIR-V code at both.