Timestamp queries on primary command buffers executing secondary command buffers

Vulkan
1

Hi There!

Im trying to use writeTimestamp on secondary command buffers from the primary command buffer with a PipelineStageFlagBits set e.g VertexShader. But for some reason no matter which stage im selecting, the timers im getting from getQueryPoolResults are the same.

My steps are:


vk::CommandBufferBeginInfo cmdBufInfo = {}; 

CmdBuffer.begin(&cmdBufInfo); 

CmdBuffer.resetQueryPool(_queryPoolTimeStamp, 0, 2); 
CmdBuffer.writeTimestamp(vk::PipelineStageFlagBits::eVertexShader, _queryPoolTimeStamp, 0);

CmdBuffer.beginRenderPass(&renderPassBeginInfo, vk::SubpassContents::eSecondaryCommandBuffers);
CmdBuffer.executeCommands(_drawBuffers.size(), _drawBuffers.data());
CmdBuffer.endRenderPass(); 

CmdBuffer.writeTimestamp(vk::PipelineStageFlagBits::eVertexShader, _queryPoolTimeStamp, 1); 

CmdBuffer.end();

And in my draw loop after the queues has been executed.

std::vector<uint64_t> timestampsNS(2); 
VulkanEngine.GetDevice().getQueryPoolResults(_queryPoolTimeStamp, 0, 2, sizeof(uint64_t) * 2, &timestampsNS[0], sizeof(uint64_t), vk::QueryResultFlagBits::e64 | vk::QueryResultFlagBits::eWait); 
UInt delta = (timestampsNS[1] - timestampsNS[0]);

But whatever I do with the flags, I always get the same delta times (non zero) … even if I set compute stage flag in the render pipeline. I checked the physical device limits and timestampComputeAndGraphics returns 64, so it should give me more detailed timestamp data between the stages.

Any ideas?

Thanks,

~Dynad

2

I checked the physical device limits and timestampComputeAndGraphics returns 64, so it should give me more detailed timestamp data between the stages.

That’s not what that means. That’s simply the number of bits of precision used by the timestamp; it says nothing about the accuracy of it or whether it allows stage-accurate timing.

From the specification:

If an implementation is unable to detect completion and latch the timer at any specific stage of the pipeline, it may instead do so at any logically later stage.

So that means that the implementation is allowed to use the same stage internally for where to latch the timer onto. Like VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT.